1. Field of the Invention
This present invention relates to a semiconductor storage device, and more particularly to a semiconductor storage device which includes a circuit which performs an operation test of a memory cell section.
2. Description of the Related Art
Various semiconductor storage devices are conventionally known, and one of such conventional semiconductor storage devices is shown in FIG. 8. Referring to FIG. 8, the semiconductor storage device shown includes a memory cell section not shown into and from which data are written and read out, and a circuit for performing an operation test of the memory cell section. The circuit for performing an operation test of the memory cell section includes an input operational amplifier 201 for receiving a signal (serial signal) of an external input data bus, a reference voltage Vref and a clock signal CLK as input signals thereto, a serial to parallel conversion circuit 202 for converting a serial signal outputted from the input operational amplifier 201 into a parallel signal, a comparison circuit 203 for converting the output of the serial to parallel conversion circuit 202 and a signal from the memory cell with each other, a parallel to serial conversion circuit 204 for converting the signal from the memory cell section from a parallel signal into a serial signal, and an outputting circuit 205 for outputting an output signal of the parallel to serial conversion circuit 204 as output data to the outside.
Operation of the semiconductor storage device having the construction described above with reference to FIG. 8 is described. A serial signal from the external input data bus is fetched into the input operational amplifier 201 in synchronism with the clock signal CLK. An output signal of the input operational amplifier 201 is inputted to the serial to parallel conversion circuit 202, by which it is converted into a parallel signal. Bit data WT0 to WT7 of the resulting parallel signal are written into the memory cell section when a control signal for a writing operation is inputted to the memory cell section.
On the other hand, if another control signal for a reading operation is inputted, then bit data RT0 to RT7 are inputted from the memory cell section to the comparison circuit 203. A test of the memory cell section can be performed by reading out the data having been written into the memory cell section and comparing the bit data RT0 to RT7 of the read out data with the bit data WT0 to WT7 which are those before written into the memory cell section, respectively. If the bit data RT0 to RT7 and the bit data WT0 to WT7 coincide with each other respectively, then it can be determined that the memory cell section is normal.
When a testing operation is not performed (when a normal operation is performed), the bit data RT0 to RT7 read out from the memory cell section are fetched into the parallel to serial conversion circuit 204 in synchronism with a loading signal (LOAD). The parallel to serial conversion circuit 204 converts the fetched bit data RT0 to RT7 into a serial signal and outputs the serial signal to the outputting circuit 205 in synchronism with the clock signal CLK. The outputting circuit 205 outputs the data inputted thereto to the external data bus.
The conventional semiconductor storage device, however, is effective only for a test with a single pattern, and where a test with a plurality of patterns (write data pattern, read data check pattern and so forth) is required, write data or read check data must be re-set, and, therefore, a long testing time is required.
It is an object of the present invention to provide a semiconductor storage device whose memory cell section can be tested in a short time.
In order to attain the object described above, according to an aspect of the present invention, there is provided a semiconductor storage device, comprising a memory cell section into and from which parallel data can be written and read out, and comparison means for selecting one of a plurality of different kinds of parallel data for comparison having different data contents from each other in response to a control signal, comparing the selected data for comparison and parallel read data read out from the memory section with each other and outputting information regarding presence or absence of coincidence between the data for comparison and the read data.
In the semiconductor storage device, when a test of the memory cell section is to be performed, a plurality of kinds of parallel data (write and read check data) for comparison are produced by the comparison section, and a selected one of the comparison data and parallel data read out from the memory cell section are compared with each other. Since a plurality of data for comparison can be prepared, the number of times of setting of data for comparison is reduced or re-setting of check data is not required, and a test of the semiconductor storage device can be completed in a short time.
According to another aspect of the present invention, there is provided a semiconductor storage device, comprising a memory cell section into and from which parallel data can be written and read out, a data select circuit for selectively outputting parallel data before written into the memory cell section or parallel data read out from the memory cell section, a parallel to serial conversion circuit for outputting the parallel data outputted from the data select circuit as first parallel data and for converting the parallel data outputted from the data select circuit into serial data to produce serial output data, an outputting circuit for outputting the serial output data from the parallel to serial conversion circuit to the outside of the semiconductor storage circuit, and a comparison circuit for selecting the first parallel data from the parallel to serial conversion circuit or second parallel data before being written into the memory section as data for comparison, comparing the data for comparison and the data read out from the memory cell section with each other, outputting a determination signal representing coincidence or incoincidence of the data compared with each other, and determining the selected data for comparison as data to be written into the memory cell section.
In the semiconductor storage device, first data for comparison are produced by the data select circuit, and second data for comparison are produced from parallel data before the parallel data are written into the memory cell section. The plurality of data for comparison correspond to a plurality of write check data and a plurality of read check data. Accordingly, the number of times of setting of data for comparison is reduced or re-setting of check data is not required, and the time required for a test of the semiconductor storage device can be reduced.